CoresComm |
Product Specification |
The IEEE 802.15.4 standard and ZigBee wireless technology are designed to satisfy the market’s need for a
low-cost, standard-based and flexible wireless network technology, which offers low power consumption,
reliability, interoperability and security for control and monitoring applications with low to moderate data rates.
The IEEE 802.15.4 standard specifies the physical (PHY) and medium access control (MAC) layers at the 868 MHz,
915 MHz and 2.45 GHz ISM bands. This core implements the major digital signal processing (DSP) part of a modem conforming to the IEEE 802.15.4 standard for the 2.45 GHz
DSSS PHY employing offset quadrature phase-shift keying (OQPSK) modulation. It contains transmitter and receiver that are independent.
The transmitter receives the PHY payload and outputs the half-sine pulse-shaped OQPSK baseband signal for the
resulting PHY protocol data unit. The receiver receives automatic-gain-controlled IF signal and outputs the detected PHY payload.
The figure below shows essential integration requirements.
IF independent: The receiver can process the input at your selected IF frequency including zero IF, provided that the input was channel-filtered and sampled properly. This is possible as a result of a featured frequency offset estimation and compensation.
Required clock/sampling frequency = four times the chip rate, i.e., 8 MHz (customizable, see core modification below).
Four-bit representation of analog input/output.
To meet the -85 dBm receiver sensitivity requirement, the maximum allowable noise figure of the RF analog front end is estimated to be 18 dB.
Small area: 1.6k and 10.5k equivalent gate counts (using a standard cell library) for the transmitter and receiver respectively.
Low power consumption: 2.82mW (in 0.18u) when receiving a packet.
ce: One bit input, the chip enable. The transmitter is active only when ce is '1'.
clk: One bit input, the transmitter clock. All synchronous logic and digital-to-analog convertors act on the rising edge of clk. The clock frequency is required to be four times the chip rate.
reset: One bit input. This pin has two functions. Together with the frame_length input described below, it may be used to reset the transmitter or to force a packet transmission.
frame_length: Seven bit input. The transmitter should be reset at power up by maintaining reset='1' and frame_length="0000000" during a rising edge of clk. On the other hand, the transmitter can be forced to transmit a packet by maintaining reset='1' with nonzero frame_length during a rising edge of clk. Then that nonzero frame_length value will be interpreted as the number of octets in the PHY payload. In addition, after such a rising edge of clk, the tx_busy output will be '1' until the packet transmission is completed.
sym_in: Four bit input representing the subsequent data symbols of the PHY payload. During tx_busy='1', the transmitter will read sym_in two times the number of octets in the PHY payload, according to the timing provided by the sym_clk output described below.
sym_clk: One bit output. During tx_busy='1', there will be a number of positive pulses at sym_clk. The pulse duration equals one clock cycle, while the number of pulses equals the number of four-bit symbols in the PHY payload. The transmitter will read sym_in for a single data symbol when clk'Event and clk='1' and sym_clk='1'.
tx_busy: One bit output indicating a packet is being transmitted. When tx_busy='1', the external circuit is required not to maintain reset='1'.
i_out: Four bit output representing the I-phase baseband pulse-shaped OQPSK signal in two's complement format.
q_out: Four bit output representing the Q-phase baseband pulse-shaped OQPSK signal in two's complement format.
ce: One bit input, the chip enable. The receiver is active only when ce is '1'.
clk: One bit input, the system clock. All synchronous logic and analog-to-digital convertors act on the rising edge of clk. The clock frequency is required to be fixed at 8 MHz.
reset: One bit input, the synchronous reset. After enabled by ce, the receiver is required to be reset by setting reset high for one clock period.
I: Four bit input representing the quantized I-phase IF signal in two's complement format.
Q: Four bit input representing the quantized Q-phase IF signal in two's complement format.
sym_out: Four bit output. Detected symbols are read here.
sym_out_valid: One bit output. A rising edge of sym_out_valid indicates that a start-of-frame delimiter immediately following a synchronization symbol has been detected, and hence the subsequent symbols detected will represent the frame length and frame data respectively. After the rising edge, there will be approximately 128 clock cycles until the next detected symbol (i.e., the first part of the frame length representation) is available by the receiver. A falling edge of sym_out_valid indicates that the last symbol of a frame has been detected. Indeed sym_out_valid='1' indicates presence of a data frame.
clk_out: One bit output. The waveform of clk_out is a quasi-periodic pulse train - the pulse duration equals one clock cycle, while the duration between the rising edges of two adjacent pulses varies around 128 clock cycles due to a timing-tracking process of the receiver. When sym_out_valid is '1', external circuit must read sym_out once every period of 128 clock cycles for a detected symbol that is available between one clock cycle before and after the rising edge of clk_out. A working example is to read sym_out when clk'Event and clk='1' and sym_out_valid='1' and clk_out='1'.
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