CoresComm |
Product Specification |
Constraint length k = 7, rate = 1/3 (default: G0=OCT"133", G1=OCT"165", G1=OCT"171")
Capable of punctured coding
3-bit soft inputs
Burst and continuous modes
High speed design, above 200 Mbps data rate on Virtex-4 FPGA
Traceback depth = 48
Fully synchronous, one decoded bit/clock
Latency = 57 clock cycles
Coding gain = 5.6 dB over AWGN channel at BER = 1e-5
Available for ASIC or FPGA
clk: One bit input, the system clock. All synchronous logic acts on the rising edge of clk.
reset: One bit input, the synchronous reset. If reset is set high during a rising edge of clk, the data inputs immediately follow the edge will correspond to only the branches extending from the zero state of the trellis, while the data inputs immediately lead the edge will correspond to only the branches ending at the zero state, and all other branches in the two related stages of the trellis are nullified. Hence, the decoding process is generally started by setting reset high one-clock before the first-symbol data inputs. In addition, reset is set high during the last tail-bit inputs in burst-mode decoding.
data_in0: Three bit input, the soft input corresponding to the generator G0. Soft input represents the strength of the hard decision in the form of quantized matched filter output. The data format is offset binary, i.e., the ascending binary patterns "000", "001", .., "011" represent respectively strongest '0' to weakest '0', while the ascending patterns "100", "101", .., "111" represent respectively weakest '1' to strongest '1'. The analog signal midpoint is between "011" and "100".
data_in1: Three bit input, the soft input corresponding to the generator G1. The data format is the same as that of data_in0.
data_in2: Three bit input, the soft input corresponding to the generator G2. The data format is the same as that of data_in0.
data_valid: Three bit input for punctured coding. Set data_valid(0/1/2) low to make data_in0/1/2 dummy.
data_out: One bit output, the decoded bit. Latency = 57 clock cycles.
For Virtex-4 xc4vlx25sf363-12, place-and-route reports maximum clock frequency of 200.40 MHz on the FPGA using 4,086 slices (equivalent gate count = 81,467) and no block RAM. For Virtex-II xc2v1000fg256-6, place-and-route reports maximum clock frequency of 135.35 MHz on the FPGA using 3,784 slices (equivalent gate count = 84,404) and no block RAM. It is important to properly set the timing constraints and related properties to obtain the reported results.
Soft input data width and traceback depth parameters can be modified, but it can result in changing of speed and latency. The branch metric front-end can be bypassed for use in trellis coded modulation.
This core is available for both ASIC and FPGA. Since CoresComm is a member of the SignOnce Common License Consortium, an FPGA license may be sold under the project or site license supported by the consortium. Contact us at sales@corescomm.com for your further information/quote.
For license with source code, deliverables include the source code and test bench in VHDL. For license without source code, an NGC netlist is provided instead of the source code. One-year full support via e-mail is included in every license.